1. Field Of The Invention
This invention relates generally to programmable logic devices, and in particular to memory cells used to define the configuration of programmable logic devices.
2. Description of the Related Art
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they are less expensive and require less time to implement than semi-custom and custom integrated circuits.
One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks, or CLBs, that are programmably interconnected to each other and to programmable input/output blocks (IOBs). This collection of configurable elements may be customized by loading configuration data into internal configuration memory cells that, by determining the state of various programming points, define how the CLBs, interconnections, and IOBs are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA from an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Typical FPGAs, for example a device of the Xilinx XC4000.TM. family of FPGAs commercially available from Xilinx, Inc., include one configuration memory cell to control each programming point. FIG. 1 illustrates an exemplary memory cell 100, which includes a conventional static memory element 101 (cross-coupled inverters) and an access transistor 105. Each of the cross-coupled inverters is typically implemented using a pair of MOS transistors, so that the total number of transistors in memory cell 100 (including access transistor 105) is five. For a more detailed discussion of the function and configuration of suitable five-transistor memory cells, see U.S. Pat. No. 4,821,233, which issued on Apr. 11, 1989, and U.S. Pat. No. 4,750,155, which issued on Jun. 7, 1988, each of which is incorporated herein by reference.
Memory cell 100 forms the basic control unit for all logic functions on the FPGA. The program state of memory element 101 determines whether a conventional pass transistor 107 conducts, and consequently whether interconnect segments 107S and 107D (connected to the respective source and drain of pass transistor 107) are electrically connected.
One way to optimize a memory cell is to eliminate the need for one or more transistors, thereby freeing up valuable chip area and allowing greater circuit density. For example, dynamic random-access memory (DRAM) cell 200, shown in FIG. 2, includes fewer transistors than memory cell 100. DRAM cell 200 is conventionally connected to a memory control circuit 202 via a memory-access line WORD and a memory-refresh line BIT to an access transistor 208. A capacitor 206 is alternatively used to store a voltage representative of a logic one (e.g., 3.3 volts) or a voltage representative of a logic zero (e.g., 0 volts); an access transistor 208 is used to write and read those voltages to and from capacitor 206.
Memory control circuit 202 conventionally includes refresh circuitry. As is well known to those of skill in DRAM technology, this refresh circuitry is needed to periodically refresh the voltage level stored by capacitor 206 because capacitor 206 loses charge over time due to leakage current. Refreshing data includes reading the stored voltage level, determining whether that level represents a logic one or a logic zero, and then restoring the voltage level to a pre-leakage level. The capacitance of capacitor 206 is selected such that some minimum level of charge is maintained between the periodic refresh cycles.
Applying conventional DRAM technology to FPGAs is problematic. Capacitor 206, if implemented laterally, occupies a substantial amount of chip area. DRAM manufacturers have successfully addressed this problem through the use of trench capacitors; unfortunately, the manufacture of trench capacitors requires complex processing techniques that are not normally required for FPGA manufacturing, which typically employs a standard CMOS process. Either alternative --increased chip area or process complexity--increases the cost of producing FPGAs.